View H5TQ2G83DFRPBC_7167807.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.1 / may. 2012 1 2gb ddr3 sdram 2gb ddr3 sdram lead-free&halogen-free (rohs compliant) h5tq2g83dfr-xxc h5tq2g63dfr-xxc h5tq2g83dfr-xxi h5tq2g63dfr-xxi h5tq2g83dfr-xxj h5tq2g63dfr-xxj h5tq2g83dfr-xxl h5tq2g63dfr-xxl * sk hynix reserves the right to change products or specifications without notice.
rev. 1.1 / may. 2012 2 revision history revision no. history draft date remark 0.01 preliminary version release july. 2011 preliminary 0.02 add temperature information in feature aug. 2011 preliminary 0.03 update operation frequency oct. 2011 preliminary 0.04 update idd 1600,1866,2133 nov. 2011 preliminary 0.05 update idd data nov. 2011 preliminary 0.06 update idd data (x8) dec. 2011 preliminary 0.07 update pakage dimension (x16) - corrected pakage dimension (page 34 , 78 balls to 96balls) dec. 2011 preliminary 0.08 update idd data feb.2012 page 24, all idd specs are completed 0.09 official version release mar.2012 deleted ?preliminary? 1.0 official version release & add l/j part apr.2012 add l/j part support 1.1 delete comments regarding idd6tc & new revised logo (hynix to sk hynix) may.2012 page 12/17/24
rev. 1.1 / may. 2012 3 description the h5tq2g83dfr-xxc, h5tq2g63dfr-xxc,h5tq2g83dfr-xxi, h5tq2g63dfr-xxi, h5tq2g83dfr- xxl,h5tq2g63dfr-xxl,h5tq2g83dfr-xxj,h5tq2g63dfr-xxj are a 2,147,483,648-bit cmos double data rate iii (ddr3) synchronous dram, ideally suited for the main memory applications which requires large memory density and high bandwidth. sk hynix 2gb ddr3 sdrams offer fully synchronous operations ref- erenced to both rising and falling e dges of the clock. while all addresse s and control inputs are latched on the rising edges of the ck (falling edges of the ck), data, data strobes and write data masks inputs are sampled on both rising and falling ed ges of it. the data paths are intern ally pipelined and 8-bit prefetched to achieve very high bandwidth. device features and ordering information features * this product in compliance with the rohs directive. ? vdd=vddq=1.5v +/- 0.075v ? fully differential clock inputs (ck, ck ) operation ? differential data strobe (dqs, dqs ) ? on chip dll align dq, dqs and dqs transition with ck transition ? dm masks write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable cas latency 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported ? programmable additive latency 0, cl-1, and cl-2 supported ? programmable cas write latency (cwl) = 5, 6, 7, 8 ? programmable burst length 4/8 with both nibble sequential and interleave mode ? bl switch on the fly ? 8banks ? average refresh cycle (tcase 0 o c~ 95 o c) - 7.8 s at 0 o c ~ 85 o c - 3.9 s at 85 o c ~ 95 o c commercial temperature( 0 o c ~ 85 o c) industrial temperature( -40 o c ~ 95 o c) ? jedec standard 78ball fbga(x8), 96ball fbga(x16) ? driver strength selected by emrs ? dynamic on die termination supported ? asynchronous reset pin supported ? zq calibration supported ? tdqs (termination data strobe) supported (x8 only) ? write levelization supported ? 8 bit pre-fetch
rev. 1.1 / may. 2012 4 ordering information * xx means speed bin grade operating frequency * xx means speed bin grade part no. configuration power consumption temperature package h5tq2g83dfr-*xxc 256m x 8 normal consumption commercial 78ball fbga h5tq2g83dfr-*xxi industrial h5tq2g83dfr-*xxl low power consumption (idd6 only) commercial h5tq2g83dfr-*xxj industrial h5tq2g63dfr-*xxc 128m x 16 normal consumption commercial 96ball fbga h5tq2g63dfr-*xxi industrial h5tq2g63dfr-*xxl low power consumption (idd6 only) commercial h5tq2g63dfr-*xxj industrial speed grade (marking) frequency [mbps] remark (cl-trcd-trp) cl5 cl6 cl7 cl8 cl9 cl10 cl11 cl12 cl13 cl14 -g7 667 800 1066 1066 ddr3-1066 7-7-7 -h9 667 800 1066 1066 1333 1333 ddr3-1333 9-9-9 -pb 667 800 1066 1066 1333 1333 1600 ddr3-1600 11-11-11 -rd 800 1066 1066 1333 1333 1600 1866 ddr3-1866 13-13-13 -te 800 1066 1066 1333 1333 1600 1866 2133 ddr3-2133 14-14-14
rev. 1.1 / may. 2012 5 x8 package ball out (top view): 78ball fbga package 1 2 3 4 5 6 7 8 9 a vss vdd nc nu/tdqs vss vdd a b vss vssq dq0 dm/tdqs vssq vddq b c vddq dq2 dqs dq1 dq3 vssq c d vssq dq6 dqs vdd vss vssq d e vrefdq vddq dq4 dq7 dq5 vddq e f nc vss ras ck vss nc f g odt vdd cas ck vdd cke g h nc cs we a10/ap zq nc h j vss ba0 ba2 nc vrefca vss j k vdd a3 a0 a12/bc ba1 vdd k l vss a5 a2 a1 a4 vss l m vdd a7 a9 a11 a6 vdd m n vss reset a13 a14 a8 vss n 1 2 3 4 5 6 7 8 9 12 a b c d e f g h j k l m n populated ball ball not populated 3 789 (top view: see the balls through the package)
rev. 1.1 / may. 2012 6 x16 package ball out (top vi ew): 96ball fbga package 1 2 3 4 5 6 7 8 9 a vddq dqu5 dqu7 dqu4 vddq vss a b vssq vdd vss dqsu dqu6 vssq b c vddq dqu3 dqu1 dqsu dqu2 vddq c d vssq vddq dmu dqu0 vssq vdd d e vss vssq dql0 dml vssq vddq e f vddq dql2 dqsl dql1 dql3 vssq f g vssq dql6 dqsl vdd vss vssq g h vrefdq vddq dql4 dql7 dql5 vddq h j nc vss ras ck vss nc j k odt vdd cas ck vdd cke k l nc cs we a10/ap zq nc l m vss ba0 ba2 nc vrefca vss m n vdd a3 a0 a12/bc ba1 vdd n p vss a5 a2 a1 a4 vss p r vdd a7 a9 a11 a6 vdd r t vss reset a13 nc a8 vss t 1 2 3 4 5 6 7 8 9 1 a b c d e f g h j k l m n populated ball ball not populated 2 789 (top view: see the balls through the package) 3 p r t
rev. 1.1 / may. 2012 7 pin functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . cke, (cke0), (cke1) input clock enable: cke high activates, and cke lo w deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for self-refresh exit. af ter vrefca and vrefdq have become stable during the power on and initia lization sequence, they must be maintained during all operations (including self-refresh). cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke, are disabled during power- down. input buffers, excluding cke, are disabled during self-refresh. cs , (cs 0), (cs 1), (cs 2), (cs 3) input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on systems with multiple ranks. cs is considered part of the command code. odt, (odt0), (odt1) input on die termination: odt (registered high) enab les termination resistance internal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, dqs and dm/tdqs, nu/tdqs (when tdqs is enabled via mode register a11=1 in mr1) signal for x4/x8 configurations. for x16 configuration, odt is applied to each dq, dqsu, dqsu , dqsl, dqsl , dmu, and dml signal. the odt pin will be ignored if mr1 is programmed to disable odt. ras . cas . we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm, (dmu), (dml) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that inpu t data during a write access. dm is sampled on both edges of dqs. for x8 device, the function of dm or tdqs/tdqs is enabled by mode register a11 setting in mr1. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register or extended mode register is to be accessed during a mrs cycle. a0 - a15 input address inputs: provide the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (a10/ap and a12/bc have additional functions, see below). the address inputs also provide the op-code during mode register set commands. a10 / ap input auto-precharge: a10 is sampled during read/write commands to determine whether autoprecharge should be performed to the acce ssed bank after the read/write operation. (high: autoprecharge; low: no autoprec harge).a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by bank addresses. a12 / bc input burst chop: a12 / bc is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (high, no burst chop; low: burst choppe d). see command truth table for details.
rev. 1.1 / may. 2012 8 reset input active low asynchronous reset: reset is active when reset is low, and inactive when reset is high. reset must be high during normal operation. reset is a cmos rail-to-rail signal with dc high and low at 80% and 20% of v dd , i.e. 1.20v for dc high and 0.30v for dc low. dq input / output data input/ output: bi -directional data bus. dqu, dql, dqs, dqs , dqsu, dqsu , dqsl, dqsl input / output data strobe: output with read data, input wi th write data. edge-aligned with read data, centered in write data. the data strobe dqs, dqsl, and dqsu are paired with differential signals dqs , dqsl , and dqsu , respectively, to provide differential pair signaling to the system during reads and writes. ddr3 sdram su pports differential data strobe only and does not support single-ended. tdqs, tdqs output termination data strobe: tdqs/tdqs is applicable for x8 dr ams only. when enabled via mode register a11 = 1 in mr1, the dram wi ll enable the same termination resistance function on tdqs/tdqs that is applied to dqs/dqs . when disabled via mode register a11 = 0 in mr1, dm/tdqs will provide the data mask function and tdqs is not used. x4/x16 drams must disable the tdqs function via mode register a11 = 0 in mr1. nc no connect: no internal electr ical connection is present. nu no use v ddq supply dq power supply: 1.5 v +/- 0.075 v v ssq supply dq ground v dd supply power supply: 1.5 v +/- 0.075 v v ss supply ground v refdq supply reference voltage for dq v refca supply reference voltage for ca zq supply reference pin for zq calibration note: input only pins (ba0-ba2, a0-a15, ras , cas , we , cs , cke, odt, dm, and reset ) do not supply termination. symbol type function
rev. 1.1 / may. 2012 9 row and column address table 2gb note1: page size is the number of bytes of data delive red from the array to the internal sense amplifiers when an active command is registered. page size is per bank, calculated as follows: page size = 2 colbits * org ? 8 where colbits = the number of column address bits, org = the number of i/o (dq) bits configuration 256mb x 8 128mb x 16 # of banks 8 8 bank address ba0 - ba2 ba0 - ba2 auto precharge a10/ap a10/ap bl switch on the fly a12/bc a12/bc row address a0 - a14 a0 - a13 column address a0 - a9 a0 - a9 page size 1 1 kb 2 kb
rev. 1.1 / may. 2012 10 absolute maximum ratings absolute maximum dc ratings dram component operat ing temperature range absolute maximum dc ratings symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v 1,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v 1,3 v in , v out voltage on any pin relative to vss - 0.4 v ~ 1.975 v v 1 t stg storage temperature -55 to +100 o c1, 2 notes: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the device at these or any other conditions above those indicated in the operational sections of this specif ication is not implied. exposure to absolute maximum rat- ing conditions for extended pe riods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must not be greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. temperature range symbol parameter rating units notes t oper normal operating temperature range 0 to 85 o c 1,2 industrial temperature range -40 to 95 o c1,3 notes: 1. operating temperature toper is the case surface temperat ure on the center / top side of the dram. for measure- ment conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specificatio ns will be supported. dur- ing operation, the dram case temperature must be maintained between 0 - 85 o c under all operating conditions. 3. some applications require operation of the dr am in the extended temperature range between 85 o c and 95 o c case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a. refresh commands must be doubled in frequency, ther efore reducing the refresh interval trefi to 3.9 s. b. if self-refresh operation is required in the extended temperature range, then it is mandatory to use the man- ual self-refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b).
rev. 1.1 / may. 2012 11 ac & dc operating conditions recommended dc operating conditions recommended dc operating conditions symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2 notes: 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together.
rev. 1.1 / may. 2012 12 idd and iddq specification pa rameters and test conditions idd and iddq measurement conditions in this chapter, idd and iddq meas urement conditions such as test load and patterns are defined. figure 1. shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt , idd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et and idd7) are measured as time-averaged currents with all vdd balls of the ddr3 sdram under test tied together. any iddq current is not included in idd currents. ? iddq currents (such as iddq2nt and iddq4r) are measured as time-averaged currents with all vddq balls of the ddr3 sdram under test tied toge ther. any idd current is not included in iddq cur- rents. attention: iddq values cannot be directly used to calculate io power of the ddr3 sdram. they can be used to support correlation of simulated io powe r to actual io power as outlined in figure 2. in dram module application, iddq cannot be measured separately si nce vdd and vddq are using one merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply: ? ?0? and ?low? is defined as vin <= v ilac(max). ? ?1? and ?high? is defined as vin >= v ihac(max). ? ?mid_level? is defined as inputs are vref = vdd/2. ? timing used for idd and iddq measurement-loop patterns are provided in table 1. ? basic idd and iddq measurement co nditions are described in table 2. ? detailed idd and iddq measurement-loop patte rns are described in table 3 through table 10. ? idd measurements are done after properly initializi ng the ddr3 sdram. this includes but is not lim- ited to setting ron = rzq/7 (34 ohm in mr1); qoff = 0 b (output buffer enabled in mr1); rtt_nom = rzq/6 (40 ohm in mr1); rtt_wr = rzq/2 (120 ohm in mr2); tdqs feature disabled in mr1 ? attention: the idd and iddq measurement-loop patterns need to be executed at least one time before actual idd or iddq measurement is started. ? define d = {cs , ras , cas , we }:= {high, low, low, low} ? define d = {cs , ras , cas , we }:= {high, high, high, high}
rev. 1.1 / may. 2012 13 figure 1 - measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load condition may be different from above] figure 2 - correlation from simulated channel io power to actual ch annel io power supported by iddq measurement v dd ddr3 sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction
rev. 1.1 / may. 2012 14 table 1 -timings used for idd and iddq measurement-loop patterns table 2 -basic idd and iddq measurement conditions symbol ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 uni t 7-7-7 9-9-9 11-11-11 13-13-13 14-14-14 t ck 1.875 1.5 1.25 1.07 0.935 ns cl 7 9 11 13 14 nck n rcd 7 9 11 13 14 nck n rc 27 33 39 45 50 nck n ras 20 24 28 32 36 nck n rp 7 9 11 13 14 nck n faw 1kb page size 20 20 24 26 27 nck 2kb page size 27 30 32 33 38 nck n rrd 1kb page size 44556nck 2kb page size 65667nck n rfc -512mb 48 60 72 85 97 nck n rfc -1 gb 59 74 88 103 118 nck n rfc - 2 gb 86 107 128 150 172 nck n rfc - 4 gb 160 200 240 281 321 nck n rfc - 8 gb 187 234 280 328 375 nck symbol description i dd0 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act and pre; command, address, bank address inputs: pa rtially toggling according to table 3; data io: mid-level; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see table 3); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 3.
rev. 1.1 / may. 2012 15 i dd1 operating one bank active-read-precharge current cke: high; external clock: on; tck, nrc, nras, nrcd, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank address inputs, data io: partially toggling according to table 4; dm: stable at 0; bank activity: cycling with on bank active at a time: 0,0,1,1,2,2,... (see table 4); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4. i dd2n precharge standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggl ing according to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output bu ffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd2nt precharge standby odt current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggl ing according to table 6; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output bu ffer and rtt: enabled in mode registers b) ; odt signal: tog- gling according to table 6; pattern details: see table 6. i dd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: en abled in mode registers b) ; odt signal: stable at 0; precharge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: en abled in mode registers b) ; odt signal: stable at 0; precharge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 symbol description
rev. 1.1 / may. 2012 16 i dd3n active standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggl ing according to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buff er and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd3p active power-down current cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd4r operating burst read current cke: high; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between rd; command, address, bank address inputs: partially toggling accord ing to table 7; data io: seamless read data burst with different data between one bu rst and the next one according to table 7; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2, 2,...(see table 7); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7. i dd4w operating burst write current cke: high; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between wr; command, address, bank address inputs: partially toggling accord ing to table 8; data io: seamless read data burst with different data between one bu rst and the next one according to table 8; dm: stable at 0; bank activity: all banks open, wr commands cycling throug h banks: 0,0,1,1,2,2,...(see table 8); output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at high; pattern details: see table 8. i dd5b burst refresh current cke: high; external clock: on; tc k, cl, nrfc: see table 1; bl: 8 a) ; al: 0; cs : high between ref; com- mand, address, bank address inputs: partially togglin g according to table 9; data io: mid_level; dm: stable at 0; bank activity: ref command every nref (see table 9); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9. i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: self-refresh operation; out- put buffer and rtt: enabled in mode registers b) ; odt signal: mid_level symbol description
rev. 1.1 / may. 2012 17 a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[ 5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) read burst type: nibble sequential, set mr0 a[3] = 0b i dd6et self-refresh current: extended temperature range (optional) f) t case : 0 - 95 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): extend- ed e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: extended tempera- ture self-refresh operation; output buff er and rtt: enabled in mode registers b) ; odt signal: mid_level i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: see table 1; bl: 8 a), f) ; al: cl- 1; cs : high between act and rda; command, address, bank address inputs: partially toggling accord- ing to table 10; data io: read data burst with di fferent data between one burst and the next one according to table 10; dm: stable at 0; bank acti vity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee table 10; ou tput buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10. symbol description
rev. 1.1 / may. 2012 18 table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act0011000000 00 - 1,2 d, d1000000000 00 - 3,4 d , d 1111000000 00 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre0010000000 00 - ... repeat pattern 1...4 until n rc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1, 2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3, 4 d , d 1111000000 f0 - ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 1.1 / may. 2012 19 table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid_level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 00000 0 0 - ... repeat pattern 1...4 until n rcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 00000000 ... repeat pattern 1...4 until nr as - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until n rc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111 0 00000 f 0 - ... repeat pattern nrc + 1,...4 until n rc + nrce - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 00110011 ... repeat pattern nrc + 1,...4 until n rc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1,...4 until *2 nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 1.1 / may. 2012 20 table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. table 6 - idd2nt and iddq2n t measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 111 1 0 0 0 0 0 f 0 - 3d 111 1 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-17 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 1111 0 0 0 0 0 f 0 - 3d 1111 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, bu t odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-17 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7
rev. 1.1 / may. 2012 21 table 7 - idd4r and iddq4r measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 00000000 1d100000000000- 2,3 d ,d 1111 0 0000 0 0 0 - 4 rd 0 1 0 1 0 0 00 0 0 f 0 00110011 5d1000000000f0- 6,7 d ,d 1111 0 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7
rev. 1.1 / may. 2012 22 table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise mid-level. b) burst sequence driven on each dq signal by write co mmand. outside burst operation, dq signals are mid-level. table 9 - idd5b measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 00000000 1d100010000000- 2,3 d ,d 1111 1 0000 0 0 0 - 4 wr 0 1 0 0 1 0 00 0 0 f 0 00110011 5d1000100000f0- 6,7 d ,d 1111 1 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 11.2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 f 0 - 5...8 repeat cycles 1...4, but ba[2:0] = 1 9...12 repeat cycles 1...4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary.
rev. 1.1 / may. 2012 23 table 10 - idd7 meas urement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2d100000000000- ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd d1000030000f0 - assert and repeat above d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-loop 1, but ba[2:0] = 7 9 nfaw+4*nrrd d1000070000f0 - assert and repeat above d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2&nfaw+2 d1000000000f0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nfaw+nrrd+ 2 d100001000000 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d100003000000- assert and repeat above d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 19 3*nfaw+4*nrrd d100007000000- assert and repeat above d command until 4* nfaw - 1, if necessary
rev. 1.1 / may. 2012 24 idd specifications idd values are for full operating range of voltage and temperature unless otherwise noted. i dd specification notes: 1. applicable for mr2 settings a6=0 and a7=0. temperature range for idd6 is 0 - 85 o c. 2. applicable for mr2 settings a6=0 and a7=1. temperature range for idd6et is 0 - 95 o c. speed grade bin symbol ddr3 - 1066 7-7-7 ddr3 - 1333 9-9-9 ddr3 - 1600 11-11-11 ddr3 - 1866 13-13-13 ddr3 - 2133 14-14-14 unit notes max. max. max. max. max. i dd0 50 55 55 60 65 ma x8 50 55 55 60 65 ma x16 i dd01 60 65 70 75 80 ma x8 60 65 70 75 80 ma x16 i dd2p0 12 12 12 12 12 ma x8/16 i dd2p1 15 15 20 20 20 ma x8 15 15 20 20 20 ma x16 i dd2n 25 25 30 30 35 ma x8/16 i dd2nt 25 25 30 30 35 ma x8 35 40 40 40 45 ma x16 i dd2q 25 25 30 30 35 ma x8/16 i dd3p 20 20 20 20 25 ma x8 20 20 20 20 25 ma x16 i dd3n 30 30 35 35 40 ma x8 30 30 35 35 40 ma x16 i dd4r 120 140 165 185 210 ma x8 120 140 165 185 210 ma x16 i dd4w 115 135 155 170 190 ma x8 115 135 155 170 190 ma x16 i dd5b 105 110 120 125 130 ma x8 105 110 120 125 130 ma x16 i dd6 normal 12 12 12 12 12 ma x8/16 low power 6.5 6.5 6.5 6.5 6.5 ma x8 6.5 6.5 6.5 6.5 6.5 ma x16 i dd6et 14 14 14 14 14 ma x8/16 i dd7 215 225 235 255 280 ma x8 215 225 235 255 280 ma x16
rev. 1.1 / may. 2012 25 input/output capacitance parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 units notes min max min max min max min max min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) c io 1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 1.4 2.2 1.4 2.1 pf 1,2,3 input capacitance, ck and ck c ck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pf 2,3 input capacitance delta ck and ck c dck 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pf 2,3,4 input capacitance delta, dqs and dqs c ddqs 0 0.20 0 0.20 0 0.15 0 0.15 0 0.15 0 0.15 pf 2,3,5 input capacitance (all other input-only pins) c i 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pf 2,3,6 input capacitance delta (all ctrl input-only pins) c di_ctr l -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 -0.4 0.2 pf 2,3,7,8 input capacitance delta (all add/cmd input-only pins) c di_add _cmd -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 -0.4 0.4 pf 2,3,9,10 input/output capacitance delta (dq, dm, dqs, dqs ) c dio -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pf 2,3,11 input/output capacitance of zq pin c zq - 3 - 3 - 3 - 3 - 3 - 3 pf 2,3,12 notes: 1. although the dm, tdqs and tdqs pins have different functions, the loading matches dq and dqs. 2. this parameter is not subject to prod uction test. it is verified by design and characterization. the capacitance is measured according to jep147(?procedure for measuring input capacitance using a vector network analyzer(vna)?) with vdd, vddq, vss,vssq applied an d all other pins floating (except the pin under test, cke, reset and odt as necessary). vdd=vddq=1.5v, vbias=vdd/2 and on-die termination off. 3. this parameter applies to monolithic devices on ly; stacked/dual-die devices are not covered here 4. absolute value of c ck -c ck . 5. absolute value of c io (dqs)-c io (dqs ). 6. c i applies to odt, cs , cke, a0-a15, ba0-ba2, ras , cas , we . 7. c di_ctr applies to odt, cs and cke. 8. c di_ctrl =c i (cntl) - 0.5 * c i (clk) + c i (clk )) 9. c di_add_cmd applies to a0-a15, ba0-ba2, ras , cas and we . 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (clk)+c i (clk )) 11. c dio =c io (dq) - 0.5*(c io (dqs)+c io (dqs )) 12. maximum external load capacitance an zq pin: 5 pf.
rev. 1.1 / may. 2012 26 standard speed bins ddr3l sdram standard speed bins include tck, trcd , trp, tras and trc for each corresponding bin. ddr3-800 speed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-800e unit notes cl - nrcd - nrp 6-6-6 parameter symbol min max internal read command to first data t aa 15 20 ns act to internal read or write delay time t rcd 15 ? ns pre command period t rp 15 ? ns act to act or ref command period t rc 52.5 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1, 2, 3, 4, 11 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3 supported cl settings 5, 6 n ck 11 supported cwl settings 5 n ck
rev. 1.1 / may. 2012 27 ddr3-1066 speed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-1066f unit note cl - nrcd - nrp 7-7-7 parameter symbol min max internal read command to first data t aa 13.125 20 ns act to internal read or write delay time t rcd 13.125 ? ns pre command period t rp 13.125 ? ns act to act or ref command period t rc 50.625 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1, 2, 3, 4, 6, 11 cwl = 6 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 6 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3 supported cl settings 5, 6, 7, 8 n ck 11 supported cwl settings 5, 6 n ck
rev. 1.1 / may. 2012 28 ddr3-1333 speed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-1333h unit note cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first data t aa 13.5 (13.125) 11 20 ns act to internal read or write delay time t rcd 13.5 (13.125) 11 ?ns pre command period t rp 13.5 (13.125) 11 ?ns act to act or ref command period t rc 49.5 (49.125) 11 ?ns act to pre command period t ras 36 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1, 2, 3, 4, 7, 11 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 7 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4, 7 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 7 (optional) 11 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 7 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3 (optional) ns 5 supported cl settings 5, 6, 8, (7), 9, (10) n ck supported cwl settings 5, 6, 7 n ck
rev. 1.1 / may. 2012 29 ddr3-1600 speed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-1600k unit note cl - nrcd - nrp 11-11-11 parameter symbol min max internal read command to first data t aa 13.75 (13.125) 11 20 ns act to internal read or write delay time t rcd 13.75 (13.125) 11 ?ns pre command period t rp 13.75 (13.125) 11 ?ns act to act or ref command period t rc 48.75 (48.125) 11 ?ns act to pre command period t ras 35 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1, 2, 3, 4, 8, 11 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 8 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4, 8 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 8 (optional) 5 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4, 8 cwl = 8 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 8 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4, 8 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 4, 8 (optional) 5 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 8 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4 cl = 11 cwl = 5, 6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1, 2, 3 supported cl settings 5, 6, (7), 8, (9), 10, 11 n ck supported cwl settings 5, 6, 7, 8 n ck
rev. 1.1 / may. 2012 30 ddr3-1866 speed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-1866m unit note cl - nrcd - nrp 13-13-13 parameter symbol min max internal read command to first data t aa 13.91 (13.125) 13 20 ns act to internal read or write delay time t rcd 13.91 (13.125) 13 ?ns pre command period t rp 13.91 (13.125) 13 ?ns act to pre command period t ras 34 9 * trefi ns act to act or pre command period t rc 47.91 (47.125) 13 -ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1, 2, 3, 4, 9 cwl = 6,7,8,9 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 9 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4, 9 cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 9 cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 9 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4, 9 cwl = 8,9 t ck(avg) reserved ns 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 4, 9 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4, 9 cwl = 9 t ck(avg) reserved ns 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 9 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4, 9 cl = 11 cwl = 5,6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1, 2, 3, 4, 9 cwl = 9 t ck(avg) reserved ns 1, 2, 3, 4 cl = 12 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) reserved ns 1,2,3,4 cl = 13 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) 1.07 <1.25 ns 1, 2, 3 supported cl settings 5, 6, 7, 8, 9, 10, 11, 13 n ck supported cwl settings 5, 6, 7, 8, 9 n ck
rev. 1.1 / may. 2012 31 ddr3-2133 speed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-2133n unit note cl - nrcd - nrp 14-14-14 parameter symbol min max internal read command to first data t aa 13.09 20.0 ns act to internal read or write delay time t rcd 13.09 ? ns pre command period t rp 13.09 ? ns act to pre command period t ras 33.0 9 * trefi ns act to act or pre command period t rc 46.09 - ns cl = 5 cwl = 5 t ck(avg) reserved ns 1, 2, 3, 4, 10 cwl = 6,7,8,9,10 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 10 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4, 10 cwl = 7,8,910 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 10 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4, 10 cwl = 8,9,10 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 10 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4, 10 cwl = 8,9,10 t ck(avg) reserved ns 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 10 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4, 10 cwl = 9,10 t ck(avg) reserved ns 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 9 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4, 9 cwl = 9 t ck(avg) reserved ns 4 cwl = 10 t ck(avg) reserved ns 4 cl = 11 cwl = 5,6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1, 2, 3, 10 cwl = 9 t ck(avg) reserved ns 1, 2, 3, 4, 10 cwl = 10 t ck(avg) reserved ns 1, 2, 3, 4 cl = 12 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) reserved ns 1,2,3,4, 10 cwl = 10 t ck(avg) reserved ns 4 cl = 13 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) 1.07 <1.25 ns 1, 2, 3, 10 cwl = 10 t ck(avg) reserved 1, 2, 3, 4 cl = 14 cwl = 5,6,7,8,9 t ck(avg) reserved ns 4 cwl = 10 t ck(avg) 0.935 <1.07 ns 1, 2, 3 supported cl settings 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 n ck supported cwl settings 5, 6, 7, 8, 9, 10 n ck
rev. 1.1 / may. 2012 32 speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); 1. the cl setting and cwl setting result in tck(avg).min and tck(avg).max re quirements. when making a selection of tck(avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely analog - data and strobe output are synchronized by the dll - all possible intermediate frequencies may not be guaranteed. an application should use the next smaller jedec stan- dard tck(avg) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculating cl [n ck] = taa [ns] / tck( avg) [ns], rounding up to the next ?supported cl?, where tck(avg) = 3. 0 ns should only be used for cl = 5 calculation. 3. tck(avg).max limits: calculate tck(avg) = taa.max / cl selected and round th e resulting tck(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to cl selected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devices in the industry to support this setting, however, it is not a mandatory fea- ture. refer to sk hynix dimm data sheet and/or the dimm spd information if and how this setting is supported. 6. any ddr3-1066 speed bin also supports fu nctional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 7. any ddr3-1333 speed bin also supports fu nctional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 8. any ddr3-1600 speed bin also supports fu nctional operation at lower frequencies as shown in the table which are not subject to production tests but ve rified by design/characterization. 9. any ddr3-1866 speed bin also supports fu nctional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 10. any ddr3-2133 speed bin also supports functional operatio n at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization 11. sk hynix ddr3 sdram devices supporting optional down bi nning to cl=7 and cl=9, and taa/trcd/trp must be 13.125 ns or lower. spd settings must be programmed to matc h. for example, ddr3-1333h devices supporting down bin- ning to ddr3-1066f should program 13.125 ns in spd byte s for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20). ddr3-1600k devices supporting down binnin g to ddr3-1333h or ddr3-1600f should program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20). once trp (byte 20) is programmed to 13.125ns, trcmin (byte 21,23) also should be programmed accordingly. for example, 49.125ns (trasmin + trpmin = 36 ns + 13.125 ns) for ddr3-1333h and 48.125ns (trasmin + trpmin = 35 ns + 13.125 ns) for ddr3-1600k. 12. for cl5 support, refer to dimm spd inform ation. dram is required to support cl 5. cl5 is not mandatory in spd coding. 13. sk hynix ddr3 sdram devices supporting optional down binning to cl=11, cl=9 and cl=7, taa/trcd/ trpmin must be 13.125ns. spd setting must be programed to match. for example, ddr3-1866m devices supporting down binning to ddr 3-1600k or ddr3-1333h or 1066f should program 13.125ns in spd bytes for taamin(byt e 16), trcdmin(byte 18) and trpmin(b yte 20) is programmed to 13.125ns, trcmin(byte 21,23) also should be programmed accord ingly. for example, 47.125ns (trasmin + trpmin = 34ns + 13.125ns)
rev. 1.1 / may. 2012 33 package dimensions package dimension(x8): 78ball fi ne pitch ball grid array outline
rev. 1.1 / may. 2012 34 package dimension(x16): 96ball fi ne pitch ball grid array outline

▲Up To Search▲

Price & Availability of H5TQ2G83DFRPBC

	To Download H5TQ2G83DFRPBC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .